INTRODUCTIONRESEARCHRECENT PROJECTSCOURSESPUBLICATIONS
Complex Digital Systems (09-2)
HOME : PREVIOUS COURSES : Complex Digital Systems (09-2)
Most of the documents referenced by this page are available in PDF format. On Athena, Mozilla is already configured with the necessary plug-in to view PDF files. To configure the browser on your machine you may need to download and install the Adobe Acrobat Reader.
1. Course Info
  • Course Info [ PDF ]
  • 2. Lectures
  • L01: Introduction [ PPT(updated) ] [ PDF(2 slides per page) ]
  • L02: IntroductionBS [ PPT(updated) ] [ PDF(2 slides per page) ]
  • L03: IFFT [ PPT(updated) ] [ PDF(2 slides per page) ]
  • L04: SynchronousPipelines [ PPT(updated) ] [ PDF(2 slides per page) ]
  • L05: Lab1 Tutorial [ PPT(updated) ] [ PDF(2 slides per page) ]
  • L06: Basics of Multirule systems [ PPT(updated) ] [ PDF(2 slides per page) ]
  • L07: Asynchonous Pipelines [ PPT(updated) ] [ PDF(2 slides per page) ]
  • L08: IPLookup [ PPT ] [ PDF(2 slides per page) ]
  • L09: Lab2 Tutorial [ PPT ]
  • L09-2: Subversion [ PPT ]
  • L10: IP Lookup 2: Completion Buffer [ PPT ]
  • L11: Basics of Multirule systems [ PPT ] [ PDF(2 slides per page) ]
  • L12: AsynchonousPipelines [ PPT ] [ PDF(2 slides per page) ]
  • Tutorial: Types in BSV [ PPT ]
  • L14: Modularity issues [ PPT ] [ PDF(2 slides per page) ]
  • L15: Modular Refinment [ PPT ] [ PDF(2 slides per page) ]
  • L16: Tutorial Lab 4 [ PPT ]
  • L17: Sequential FSMs - StmtFSM [ PPT] [ PDF(2 slides per page)]
  • L18: MatrixMultiply_clipped [ PPT] [ PDF(2 slides per page)]
  • L19: MatrixMultiply [ PDF(2 slides per page)]
  • L20: MultipleClockDomains-1 [ PPT ] [ PDF(2 slides per page)]
  • L21: MultipleClockDomains-2 [ PPT ] [ PDF(2 slides per page)]
  • L22: LI_BDN-1 [ PPT ] [ PDF(2 slides per page)]
  • L23: LI_BDN-2 [ PPT ] [ PDF(2 slides per page)]
  • L24: Processor Labs [ PPT ]
  • L25: Sorting [ PPT ]
  • L28: RevistingProcessorsLabs[ PPT ][ PDF ]
  • L29: Semantics [ PPT ][ PDF ][ Scheduling Paper ]
  • 3. Labs
  • Lab01 : A Simple Audio Pipeline [PDF]
  • Lab02 : Fast Fourier Transforms [PDF]
  • Lab03 : Simple Audio Signal Manipulation [PDF]
  • Lab04 : A Pipelined SMIPSv2 Processor [PDF]
  • Lab05 : A Non-Blocking Instruction Cache [PDF]
  • Lab06 : Hardware-based Sorting [PDF]
  • 4. Lab Virtual Machine
    The Lab virtual machine can be downloaded from MIT [ here ], but we have reports that this does not work in Internet Explorer. Alternatively, you can get the VM by ftping to ftp://hyewon.snu.ac.kr and logging in anonymously (username: "anonymous" and empty password).
    5. Tutorials
    The following tutorials show how to use the 6.375 toolflow on Athena/Linux. See 6.375 Athena Computing Resources for more information on the computing resources available for the class.
  • T01: Simulating Verilog RTL Using Synopsys VCS [ PDF ]
  • T02: Using CVS to Manage Source RTL [ PDF ]
  • T08: GAA-to-RTL Synthesis using the Bluespec Compiler [ PDF ]
  • T09: RTL-to-Gate Synthesis using the SynplifyPro [ PDF ] [ SRC ]
  • T10: Synthesis and Place and Route using Quartus II [ PDF ]
  • T11: System Building with SOPC Builder [ PDF ]
  • T12: Embedded Programming with the NIOS II IDE [ PDF ]
  • T13: Importing IP into SOPC Builder [ PDF ]