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[ܱ߰] Bluespec   ý 

̼  l  2010 . 12 . 23

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Bluespec ý

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̷ : Professor Arvind (MIT ±/SNU WCU ±)

ǽ : Kermin Elliott Fleming (MIT EECS ڻ),

Alfred Man Cheuk Ng (MIT EECS ڻ)

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ܱ ¿ Bluespec ϵ  Ȱ ý Ǹ Ѵ. Bluespec ý 踦 ο ϵ , ϵ ޸ Ʈ Ư äϿ parameterized descriptions of designs, correctness-by-construction, modular refinement, ׸ IP ϵ Ѵ. Bluespec Ϸ ڰ ۼ RTL ڵ忡 ȭ RTL ڵ带 ָ, ̷ ڵ ASIC FPGA ٷ ִ. Bluespec а迡 H.264, ȣȭ/ȣȭ , 802.11 , SSD Ʈѷ, ׸ Ƽھ PowerPC ϴµ а Ȱǰ ִ. Bluespec SoC , 𵨸, ռ ǰ FPGA μ Ŭ ùķ̼ǿ Ȱǰ ִ.

ܱ ´ پ Ͽ Bluespec  ֵ Ǿ ִ. ´ ũ ̷ ǿ ǽ Ǿ , ǽ MIT п ȹ̴. Ư 4ȸ ǽ Ͽ Bluespec Ȱ ý 踦 ɵ ְ ȴ.

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ܱ ´ MIT ± б WCU ؿû Arvnid Ѵ. Arvind ̱Ѹ(National Academy of Engineering) ȸ MIT ǻ ΰ (CSAIL, Computer Science and Artificial Intelligence Laboratory) åڷμ Ȱ ̴. Ⱓ ǻ о ڷμ ޾, ǻ о ְ ִ IEEE Fellow, ACM Fellow Ȱϰ ִ. Arvind 1969 ڰ л縦 Indian Institute of Technology, Kanpur ް, University of Minnesota ǻ , ڻ 1972, 1973⿡ ޾Ҵ. ̵غ University of California, Irvine 1979ʹ MIT ϰ , 1985 CSAIL Computation Structures Group ռ Ȱ ϰ ִ.

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Bluespec is a new way of describing the behavior of complex digital systems using guarded atomic actions. It has many features of advanced software languages and facilitates parameterized descriptions of designs, correctness-by-construction, modular refinement and IP reuse. Bluespec compiler generates structural RTL, which is competitive with hand-coded RTL and which can be targeted to ASICs and FPGAs using commercial tools. Bluespec tools are mature and have been used both in industry and academia to design complex digital systems including video CODEC H.264, encryption/decryption modules, wireless base-band processing (802.11), SSD controller and multicore PowerPC. Bluespec is also being used in verification and testing, modeling and synthesis of Systems on a chip and in cycle-accurate simulation of processors on FPGAs.


This 5-day intensive course will introduce Bluespec via examples chosen to illustrate important aspects of digital design.  The participants will get hands-on experience in using Bluespec in four accompanying laboratory exercises. The course format will be two lectures before lunch followed by laboratory exercises in the afternoon on participants own laptop computers.  Expert help will be available during the laboratory hours.


The course is intended for practicing engineers and graduate students. Minimal knowledge of digital design is assumed but some familiarity with simple processor pipelines is necessary to follow the lectures. Participants should be able to start on their own designs in Bluespec after completing this course. The preliminary outline of the course is as follows:



M.1 – Introduction to Bluespec: Understanding guarded atomic actions and hardware synthesis using GCD as an example

M.2 – Introduction to combinational circuits and simple inelastic pipelines using FFT

Lab1 – Design a simple FIR filter



T.1 – More on inelastic pipelines and single-rule systems

T.2 – Simple Elastic pipelines

Lab2 – Two implementations of FFT



W.1 – Concurrency issues in multi-rule systems using IP-Lookup

W.2 – Modeling in-order processor pipelines

Lab3 – Complete the implementation of a partially specified SMIPS processor


Th.1 – Elastic pipelines for processors

Th.2 – Modular refinement – replacing a module by another with different timing characteristics

Lab4 – A working pipelined SMIPS.


F.1 – Introduction to hardware-software codesign using Vorbis audio decoder

F.2 – Introduction to  hardware-software infrastructure issues – how to make it all work.

Lab5 – Various demos on FPGAs to be conducted by Teaching Assistants



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